Power Optimized and Reliable Modified Edge Preserving Architecture for Noise Aware Preprocessing Applications

Abstract

The rising use of System-on-Chip (SoC) technology in the fields of embedded vision, surveillance, biomedical imaging
and portable electronic devices has produced a growing demand for high performance and low power image preprocessing systems. Random-valued impulse noise is one of the many variables that degrades images and severely degrades the quality of the collected binary image data, which badly affects future image analysis and processing operations. This work proposes an efficient SoC based architecture to remove the random valued impulse noise from the collected binary data in order to overcome this problem. The decision-tree-based detector to detect the noisy values and employs an effective design to locate the edge is proposed in this design. Decision tree based hybrid integrated de-noising method (DTHIDM) is used as proposed methodology for this project to implement efficient de-noising process. If there are noisy values, edges, or blocks in this region, the distribution of the values is different. Therefore, we determine whether current pixel is an Seclusion point by observing the smoothness of its surrounding pixels. The noise may seriously affect the performance of image processing techniques. Hence, an efficient denoising technique becomes a very important issue in data processing.