Design of Sub-Threshold Adders Using Schmitt Trigger Logic for Ultra-Low-Power Applications

Abstract

Interest in sub-threshold computing has increased due to the growing need for ultra-low-power portabledevices and the spike in need for self-powered or energy-harvesting systems. However, due to their reduced supply voltage, these circuits face challenges, making them susceptible to noise and process variations. Schmitt trigger (ST) logic-based design is an effective strategy to reinforce the reliability of circuits in noisy situations by improving noise margin and lowering leakage current. In this work different adders, such as the Weinberger and Ling adders, can be created using ST logic in subthreshold region and these adders offer less power consumption and delay. These adders utilize parallel architecture which minimizes the overall processing delay and in addition with that the ling adder adopts a Pseudo-carry logic which lessensthe circuit complexity. This reduction in logic stages allows for the fastest computation of the final carry relative to other VLSI adder implementations.