Design 20 Bit Pipeline Analog to Digital Converter on 90 NM Using Complementary Metal-Oxide-Semiconductor

Ritesh Gupta; R. S. Gamad

doi:10.5750/ijme.v168iA4(S).1914

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Published: Oct 10, 2026

DOI: https://doi.org/10.5750/ijme.v168iA4(S).1914

Keywords:

Pipeline ADC CMOS Op-Amp S/H circuit Folded Op Amp cadence tool

Ritesh Gupta

Shri G.S. Institute of Science and Technology, India, IPS Academy, IES, India

R. S. Gamad

Shri G.S. Institute of Science and Technology, India

Abstract

This paper presented a 20-bit, 20 MS/s Pipeline Analog to Digital converter (ADC) implemented on a 90nm technology of CMOS. It includes Flash ADC, Digital to Analog converter (DAC), sample and hold circuit(S/H) and other circuitry. First and foremost, the design of 4-bit flash ADC is based on novel architecture which has 4 inputs and 2 output operational amplifier (Op-Amp). This circuit minimizes the required op-amps in conventional Flash ADC. Furthermore, sample & hold circuit is design in such a way that the rate of the sample per signal is double. Since it is accompanied in this architecture of ADC, so it is enhancing the conversion speed. The proposed design is obtain 20 bit pipeline ADC by using 7 stages with 4 bit per stage. This design is working at 1 kHz input frequency which is suitable for biomedical application. The obtain results are 154.57 dB SFDR, Effective Number of Bit is 18.75 Bit, differential nonlinearity (DNL) is + 0.4 LSB as max,-0.18 LSB as min and 16.7mW average power consumption with 1.8 V supply.

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Vol. 168 No. A4(S) (2026): Special Issue: International Conference of Advance Research and Innovation

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